The integral analog-to-digital converter (ADC) is widely used in chips, especially in sensor chips, because of its simple structure and high accuracy. However, due to the disadvantage of slow conversion rate, it is often necessary to make some improvements to the traditional integrated ADC to meet the needs of the system. Such improvements usually sacrifice the performance of one aspect of the ADC in exchange for the improvement of the performance of the other aspect, in the hope that the whole system can show better performance.
FIG. 1 is a schematic structural diagram of a conventional integral ADC, which is mainly composed of a comparator (COMP), a counter (COUNTER) and a memory (RAM) which may be required to store digital signals. The working principle of the conventional integral ADC is as shown in FIG. 2, wherein the VIN represented by the heavy line is an input signal of the ADC, the VRAMP represented by the fine line is a reference voltage signal of the ADC. Where the t1 is the starting time of the timing cycle, the t2 is the moment when the voltage of the VRAMP starts to rise over time, the t3 is the time when the input voltage of the VIN and the VRAMP intersect, and the t4 is ending time of the VRAMP voltage rises with time. The voltage rise range of the VRAMP from t2 to t4 is indicated by VFS, which is the full-scale input range of the ADC. The t5 is the end of the timing cycle, and one cycle of the ADC conversion period is from t1 to t5, namely time T. The effective analog input voltage of the ADC is the difference between the voltage of the VIN signal and the initial voltage of the VRAMP signal (that is, the constant voltage at time t1˜t2), and is indicated by Δ VIN. The counter in the ADC starts to count from 0 at the time t2 with a fix clock (set as CLK) until the time t3 when the comparator flips, if the effective input signal is ΔVIN, the output of the ADC is:
                    DN        =                                                            t                ⁢                                                                  ⁢                3                            -                              t                ⁢                                                                  ⁢                2                                                    1              /              CLK                                =                                                    Δ                ⁢                                                                  ⁢                VIN                            VFS                        *                          2              N                                                        
Wherein the N is the resolution of the ADC.
Finally, the input/output transfer characteristics of the ADC can be expressed as:ΔVIN=kv*DN  {circle around (2)}
Wherein the ΔVIN is an input signal, the DN is a digital code which is finally converted by the ADC, and the kv is a fixed coefficient, which is determined by the resolution and the input full scale of the ADC (the VFS/2N in the formula {circle around (1)}).
FIG. 3 is a conventional generation mode of the reference voltage VRAMP in FIG. 2, that is, using an integrator or a digital-to-analog converter (DAC). The integrator or the DAC generally comprises an input reference voltage VREF, an output VOUT and an input sequential signal (not shown in the figure). The output voltage VOUT is controlled by the sequential signal to be a constant initial voltage or a voltage signal which changes linearly with time, the output voltage VOUT is the reference voltage VRAMP of the integral ADC, and when the reference voltage VRAMP changes linearly with the time, the formula is given as follows:VRAMP=k*Vref*t  {circle around (3)}
Wherein, the Vref is the input reference voltage of the integrator or the DAC, and which is a constant value, the t is the time, the k is a constant coefficient, and the coefficient is related to the parameter setting of the integrator or the DAC. The input/output transfer characteristic of the integral ADC using the reference voltage is shown in a formula {circle around (2)}).
The conversion rate of the integral ADC is slow due to the working principle of the integral ADC. To increase the conversion rate, the prior art is shown in FIG. 4, the conversion rate of the integral ADC is improved by changing the waveform of the reference voltage VRAMP of the ADC. That is, compared with the conventional VRAMP waveform shown by the fine line in the graph, the VRAMP waveform shown by the gray line in the graph is changed. The VRAMP waveform showed by the gray line is a polygonal line during the integration stage, which is changed from a straight line by changing the slope of the VRAMP during the integration stage. The generation mode of the VRAMP is generally to add a control signal in a conventional integrator or DAC circuit, at the set time point, the slope of the output voltage VRAMP is changed by the control signal in the integration phase. The input/output transfer characteristic of the integral ADC using the reference voltage VRAMP can be changed, and the conventional ADC transfer characteristic shown in the formula {circle around (2)} can be demodulated through a cascade digital signal processing system. Therefore, the turning point of the polyline and the slope of the VRAMP should be known in the digital processing system. Because usually there are many turning points, the conversion rate of the ADC can be increased (the conversion period of the ADC can be shortened from the original T as shown in figure to T1). Nevertheless, the above implementation mode is relatively complex, is not easy to expand, and the voltage change of the VRAMP at the turning points of the polyline are not ideal, so that the linearity of the finally-restored ADC transfer characteristic is poor.